(a) Field of the Invention
The present invention relates to a heterojunction bipolar transistor and a method of fabricating the same. More specifically, the present invention relates to a heterojunction bipolar transistor using a compound semiconductor and a method of fabricating the same.
(b) Description of the Related Art
A heterojunction bipolar transistor using a compound semiconductor such as GaAs and InP is actively used as an essential element having various functions for communications because the heterojunction bipolar transistor has very high speed, very high frequency, large current driving capability, signal linearity, and uniform operation voltage. For instance, the heterojunction bipolar transistor is used as a high-efficiency large-power amplifier in an output amplifier of a mobile terminal. Furthermore, a mixed signal heterojunction bipolar transistor technique greatly affects the construction of an optical communication system. The heterojunction bipolar transistor is disclosed in Korean Patent No. 347520. FIG. 1 is a cross-sectional view of the heterojunction bipolar transistor.
To fabricate the heterojunction bipolar transistor shown in FIG. 1, a sub-collector layer 102, a collector layer 103, a base layer 104, an emitter layer 105, and an emitter cap layer 106 are sequentially epitaxial-grown on a compound semiconductor substrate 101. An emitter electrode 111 is formed on the emitter cap layer 106. Then, the emitter cap layer 106 and the emitter layer 105 are etched into a mesa, and base electrodes 112 are formed on the base layer 104. Subsequently, the base layer 104 and the collector layer 103 are etched into a mesa, and collector electrodes 113 are formed on the sub-collector layer 102. Then, a predetermined isolation region is defined, and a dielectric insulating layer 121 is formed on the overall surface of the substrate. Finally, via holes are formed in the insulating layer 121 to expose the emitter, base, and collector electrodes, and a metal 122 is deposited or plated on the exposed emitter, base, and collector electrodes to form transmission lines. The transmission lines 122 are connected to other active or passive elements of the transistor.
In the above-described conventional method of fabricating the heterojunction bipolar transistor, the dielectric insulating layer 121 forms interfaces with the side of the emitter mesa, the side of the base-collector mesa, the exposed portion of the surface of the emitter layer, the exposed portion of the surface of the base layer, and the exposed portion of the surface of the sub-collector layer. The dielectric insulating layer 121 is formed of SiO2, Si3N4, or SiOxNy. However, recombination sites are formed at the interface of the compound semiconductor and the dielectric insulating layer because bonding coherence or smooth transition between the compound semiconductor and the dielectric insulating layer is difficult to form at the interface. This reduces a current gain of the bipolar transistor.
FIGS. 2a and 2b respectively show DC current gains before and after deposition of a SiNx dielectric insulating layer of a heterojunction bipolar transistor having an InP emitter layer and an InGaAs base layer. FIGS. 2a and 2b show a collector current Ic, a base current Ib, and a current gain according to a variation in a base-emitter voltage Vbe. The current gain corresponds to a value obtained by dividing the collector current Ic by the base current Ib. As shown in FIGS. 2a and 2b, the current gain after deposition of the SiNx dielectric insulating layer is considerably reduced as the base current Ib is increased, compared to the current gain before deposition of the SiNx insulating layer. This is because of a strong interaction of the insulating layer and an extrinsic base surface having a large surface recombination rate due to a high doping concentration (1019 to 1020 cm−3), such as at the side of the base-collector mesa and the exposed portion of the surface of the base layer. The surface recombination effect becomes stronger as the size of the transistor is decreased in order to improve the performance of the transistor.
To reduce the interface effect, a conventional technique has employed interface control layers. Specifically, a method of forming an interface layer between a compound semiconductor and an insulating layer was used. The interface layer is formed of one of the following combination layers.
1) Oxide or insulator interface control layers such as Al2O3/In(PO3)3/InP, SiO2/ECR oxide/InP, SiNx/anodic oxide/InP, and SiNx/PN/sulfur-treated InP.
2) Interface control layers including sulfur such as SiO2/S/InP, SiO2/SiS2/InP, Si3N4/polysulfide/InP, and SiNx/InS/InP.
3) Interface control layers using an ultra thin Si layer such as SiO2/Si/InGaAs, Si3N4/Si/InGaAs, SiO2/Si3N4/Si/InGaAs, SiO2/Si/InP, and Si3N4SiNx/Si/InP.
Although the conventional interface control layer forming technique appropriately compensates a difference between the compound semiconductor and the insulating layer to prevent interface characteristic from being abruptly varied, the conventional technique is not an appropriate method for solving the aforementioned problem. That is, the problem caused by the surface recombination effect is not solved because of non-continuity between the compound semiconductor and interface control layer and between the interface control layer and the insulating layer.